As a technique for improving the efficiency of developing a processor that is becoming complicated, there is a processor synthesis technique which defines a pipeline structure and an instruction set of a processor by using a special language and outputs a register transfer level (RTL) description. The RTL description is a description that expresses a circuit operation by a combination of data transfer between registers and a logical operation using a hardware description language such as Verilog or VHDL.
An increase in special instructions increases circuit resources such as operators implementing the special instructions. Even when an instruction is not executed, power is consumed because the clock and power are supplied to an operator used in the instruction. Thus, the power consumption increases with the increase in the special instructions.
As a conventional technique for designing a low power circuit, there is a method that focuses on the relationship among a condition determination unit, non-competitive data flow units, and a multiplexer unit within a circuit and adds a clock gating circuit to a circuit unit in the non-competitive data flow units which is unnecessary depending on the condition (refer to Patent Literature 1, for example).